SemiAnalysis Dissects Huawei Kirin 9030: Process Constraints Pave the Way for Foldables

In the field of semiconductor reverse engineering, TechInsights has dominated for decades. Last weekend, Dylan Patel's SemiAnalysis officially released the first public teardown report from its STEEL Lab (Teardown Engineering & Evaluation Lab), targeting one of the world's most-watched chips: the Kirin 9030 Pro, featured in the Huawei Mate 80 Pro and manufactured on SMIC's most advanced N+3 process node.

The timing is intriguing. TechInsights is currently being sold by its private equity owners, while SemiAnalysis's revenue has already surpassed this long-established giant. Dylan chose this moment to make his move, delivering a highly technical teardown report complemented by real chip photos from his Oregon lab.

The report's headline is a bombshell: SMIC N+3's minimum metal pitch (M0 pitch) is only 32.5nm, smaller than the 36nm pitch of Intel's latest 18A process used in the Panther Lake processor.

So, without EUV lithography equipment, SMIC has achieved a finer metal pitch than Intel?

Just reading this headline might send shockwaves through the entire semiconductor industry, but SemiAnalysis itself poured cold water on it in the second paragraph of the report, calling it a "cherry picked metric."

This article will interpret this teardown report for you.

Density Parity at a High Cost

SMIC's N+3 process has indeed matched TSMC's N6 in terms of transistor density.

Through TEM (Transmission Electron Microscope) cross-section analysis, the STEEL Lab measured N+3's Bohr density at 113.4 MTr/mm², slightly higher than TSMC N6's 107.7 MTr/mm². Cell height was reduced from 252nm for N+2 to 228nm, and contacted gate pitch (CGP) shrunk from 63nm to 57nm. Taken together, these figures mean that SMIC has achieved a logic density comparable to TSMC's mature 7nm-class technology using only DUV lithography, without EUV.

What's the cost?

SMIC's M0 layer uses Self-Aligned Quadruple Patterning (SAQP), which involves processing a single mask pattern four times to achieve finer lines. TSMC N6 only requires Self-Aligned Double Patterning (SADP) for the same layer. Quadruple patterning means more masks, tighter overlay accuracy requirements, more complex processing steps, and significantly higher costs.

In the cross-section images, SemiAnalysis directly observed the cost of SAQP: N+3's M0 trench exhibits a distinct trapezoidal profile (narrower at the bottom than the top), with a clear barrier layer enrichment band at the bottom of the trench. While this morphology aids copper filling, process control becomes drastically more difficult at the 32.5nm pitch.

Using an analogy a trader would understand: SMIC is printing banknotes of the same denomination, but the cost per note is several times higher than TSMC's, and the yield risk is greater. The density is the same, but the economics are completely different.

Kirin 9030: Squeezing Every Drop of Performance from Limited Silicon

Huawei HiSilicon's chip design capability is a story of a different dimension.

Looking at die size, the Kirin 9030 is almost identical to its predecessor, the 9020 (approximately 140mm²), but it packs in much more: the CPU configuration upgraded from 1 large core + 3 medium cores to 1 large + 4 medium, GPU compute units increased from 4 to 6, the NPU gained an additional Tiny core, and all levels of cache were expanded. The density improvement of N+3 allowed Huawei to fit more logic units into the same chip footprint.

In terms of performance, the STEEL lab cited public benchmark scores, offering a clear positioning: the Kirin 9030's GPU performance (Maleoon 935) roughly matches the flagship level of 2022. The 3DMark WLE score is 70% higher than the previous generation, slightly exceeding the Snapdragon 8+ Gen 1, but trails the current flagship Snapdragon 8 Elite Gen 5 by a factor of 2.4 to 2.6 times.

The CPU's situation is even more indicative. The large TaiShan Prime core's Instructions Per Clock (IPC) is roughly at the level of Arm's Cortex-X2, a 2021 design. Apple's M1 Firestorm core, released in 2020, still holds a 35% IPC advantage. The latest Apple M5 P core has a 60% IPC advantage, resulting in 2.7 times the absolute performance.

The root cause of the gap isn't design; it's the manufacturing process. Apple and Qualcomm use TSMC's N4 and N3P processes, which offer fundamental advantages in the voltage-frequency curve: more transistors can fit in the same area, and higher frequencies can be achieved at the same power consumption. Huawei's core design level is comparable to the previous generation of the industry's best, but it is trapped in a manufacturing process that is two generations old.

When Process Scaling Stalls, Huawei Turns to "Folding"

The most forward-looking part of the report is the tau scaling law and LogicFolding roadmap that Huawei presented at the 2026 ISCAS conference.

Traditional semiconductor scaling advances on a two-dimensional plane: making transistors smaller and metal lines finer. Moore's Law has operated this way for decades. Huawei's proposed tau scaling shifts the optimization target from the spatial domain to the time domain, focusing on reducing the time cost of data movement and processing, including transistor switching delay, signal propagation delay, and compute-memory latency.

LogicFolding is the engineering implementation of this theory. Simply put, it splits a logic block into two layers, stacks them face-to-face, and connects them using ultra-fine-pitch hybrid bonding. The direct benefit is shortening the longest signal paths. In modern chips, a significant portion of power consumption and delay is spent driving long interconnects and repeaters. By folding logic vertically, critical paths become shorter, allowing frequency to increase and power consumption to decrease.

Huawei laid out an aggressive roadmap: The large core frequency of the Kirin 9030 is 2.75GHz, but they have already demonstrated chips in the lab running at 3.39GHz, with a target of reaching 5GHz by 2031. Simultaneously, through 3D stacking, they aim to push the equivalent density to 295 MTr/mm², comparable to TSMC's 14A-class level.

SemiAnalysis remains cautious about this. They point out that Huawei's density calculation method differs from traditional foundries: 3D stack density is calculated based on package area. Stacking multiple active logic layers naturally yields higher numbers. Using the same method for AMD's MI450X (N2 top layer + N3P bottom layer) would yield a theoretical density of 460.2 MTr/mm², far surpassing Huawei's 2031 target.

Nevertheless, the direction itself is worth attention. By pursuing this path, Huawei is, under the constraint of limited process technology, essentially taking on the work of a foundry within a system design company. AMD puts 3D V-Cache on its cache chips, AMD MI350X moves I/O and interconnects to a base die. Huawei is going further by splitting the same logic block directly and distributing it vertically—a challenge of a completely different order of engineering difficulty.

Export Controls Have Reshaped the Dimensions of Competition

SemiAnalysis's final conclusion is blunt: Export controls have not stopped China's chip progress, but they have changed the path and the cost of that progress.

SMIC's N+3 proves that N6-class logic density is achievable without EUV. But this path is more costly, the process is more complex, and yield control is more difficult. Moving forward, the marginal difficulty of each step increases: more masks, tighter overlay accuracy, more expensive multi-patterning. Theoretically, N+4 could reach 137.8 MTr/mm² (comparable to TSMC N5), and N+5, if it incorporates backside power delivery, could even approach the HP library density of Intel 18A. But each step is harder, more expensive, and allows a smaller margin for error than the last.

At the same time, SMIC's N+2 and N+3 processes are being transferred to Hua Hong. Design companies like Alibaba's T-Head and Cambricon are also potential beneficiaries. The diffusion of chip manufacturing knowledge from a single foundry to the broader ecosystem further dilutes the effectiveness of sanctions targeting any single company.

On the design side, Huawei and Peking University are already developing domestic EDA tool prototypes for LogicFolding. This doesn't mean replacing the complete toolchains of Synopsys and Cadence, but domestic EDA is evolving towards a direction of "architecture-process-packaging co-optimization."

An interesting detail: STEEL discovered in its teardown that the DRAM in the Kirin 9030 Pro comes from Samsung (K4L2E165YD, LPDDR5X-9600, 1a process node), while the 16GB Pro Max version includes packaging from both Samsung and ChangXin Memory Technologies (CXMT). CXMT's chips bear a package date marking of Week 45, 2025, with a density comparable to the industry's 1z-class level. This indicates that Chinese memory chips have entered Huawei's flagship supply chain, even though the process node still lags behind Samsung and SK Hynix by one to two generations.

For investors, the truly noteworthy signal to track is whether Huawei's 3D stacking roadmap can allow China-produced chips to achieve a "good enough" threshold for applications like smartphones, AI inference, and networking equipment—all while keeping costs manageable.

Once "good enough" is established, the strategic value of this supply chain will be subject to repricing.